tm may2012 fdp5n50u / fdpf5n50ut n-channel mosfet, frfet ?2012 fairchild semiconductor corporation fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 1 ultra frfet tm fdp5n50u / fdpf5n50ut n-channel mosfet, frfet 500v, 4a, 2.0 features ?r ds(on) = 1.65 ( typ.)@ v gs = 10v, i d = 2a ? low gate charge ( typ. 11nc) ? low c rss ( typ. 5pf) ? fast switching ? 100% avalanche tested ? improved dv/dt capability ? rohs compliant description these n-channel enhancement mode power field effect transis- tors are produced using fairchild?s proprietary, planar stripe, doms technology. this advance technology has been especially tailored to mini- mize on-state resistance, prov ide superior switching perfor- mance, and withstand high energy pulse in the avalanche and commutationmode. these devices are well suited for high effi- cient switched mode power supplies and active power factor cor- rection. d g s to-220 fdp series g d s to-220f fdpf series (potted) g s d mosfet maximum ratings t c = 25 o c unless otherwise noted* thermal characteristics symbol parameter fdp5n50u fdpf5n50ut units v dss drain to source voltage 500 v v gss gate to source voltage 30 v i d drain current -continuous (t c = 25 o c) 4 4* a -continuous (t c = 100 o c) 2.4 2.4* i dm drain current - pulsed (note 1) 16 16* a e as single pulsed avalanche energy (note 2) 216 mj i ar avalanche current (note 1) 4 a e ar repetitive avalanche energy (note 1) 8.5 mj dv/dt peak diode recovery dv/dt (note 3) 20 v/ns p d power dissipation (t c = 25 o c) 85 28 w - derate above 25 o c0.670.22w/ o c t j , t stg operating and storage temperature range -55 to +150 o c t l maximum lead temperature for soldering purpose, 1/8? from case for 5 seconds 300 o c symbol parameter fdp5n50u fdpf5n50ut units r jc thermal resistance, junction to case 1.4 4.5 o c/w r cs thermal resistance, case to sink typ. 0.5 - r ja thermal resistance, junction to ambient 62.5 62.5 *drain current limited by maximum junction temperature
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 2 package marking and ordering information t c = 25 o c unless otherwise noted electrical characteristics off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics device marking device package reel size tape width quantity fdp5n50u fdp5n50u to-220 - - 50 fdpf5n50ut fdpf5n50ut to-220f - - 50 symbol parameter test conditions min. typ. max. units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0v, t j = 25 o c 500 - - v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 o c-0.7-v/ o c i dss zero gate voltage drain current v ds = 500v, v gs = 0v - - 25 a v ds = 400v, t c = 125 o c - - 250 i gss gate to body leakage current v gs = 30v, v ds = 0v - - 100 na v gs(th) gate threshold voltage v gs = v ds , i d = 250 a3-5v r ds(on) static drain to source on resistance v gs = 10v, i d = 2a - 1.65 2 g fs forward transconductance v ds = 40v, i d = 2a (note 4) -4.8-s c iss input capacitance v ds = 25v, v gs = 0v f = 1mhz - 485 650 pf c oss output capacitance - 65 90 pf c rss reverse transfer capacitance - 5 8 pf q g(tot) total gate charge at 10v v ds = 400v, i d = 4a v gs = 10v (note 4, 5) -1115nc q gs gate to source gate charge - 3 - nc q gd gate to drain ?miller? charge - 5 - nc t d(on) turn-on delay time v dd = 250v, i d = 4a r g = 25 (note 4, 5) -1438ns t r turn-on rise time - 21 52 ns t d(off) turn-off delay time - 27 64 ns t f turn-off fall time - 20 50 ns i s maximum continuous drain to source diode forward current - - 4 a i sm maximum pulsed drain to source diode forward current - - 16 a v sd drain to source diode forward voltage v gs = 0v, i sd = 4a - - 1.6 v t rr reverse recovery time v gs = 0v, i sd = 4a di f /dt = 100a/ s (note 4) -36-ns q rr reverse recovery charge - 33 - nc notes: 1: repetitive rating: pulse width limi ted by maximum junction temperature 2: l = 27mh, i as = 4a, v dd = 50v, r g = 25 , starting t j = 25c 3: i sd 4a, di/dt 200a/ s, v dd bv dss , starting t j = 25c 4: pulse test: pulse width 300 s, duty cycle 2% 5: essentially independent of operating temperature typical characteristics
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 3 typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo ltage variation vs. source current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 45678 0.1 1 10 150 o c *notes: 1. v ds = 20v 2. 250 s pulse test 25 o c i d ,drain current[a] v gs ,gate-source voltage[v] 0.1 1 10 0.1 1 10 30 *notes: 1. 250 s pulse test 2. t c = 25 o c v gs = 15.0v 10.0v 8.0 v 7.0 v 6.5 v 6.0 v 5.5 v i d ,drain current[a] v ds ,drain-source voltage[v] 0.02 0 6 12 18 1.4 1.8 2.2 2.6 *note: t j = 25 o c v gs = 20v v gs = 10v r ds(on) [ ] , drain-source on-resistance i d , drain current [a] 0.4 1.0 1.6 2.2 1 10 *notes: 1. v gs = 0v 2. 250 s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 30 0.1 1 10 0 200 400 600 800 1000 c oss c iss c iss = c gs + c gd ( c ds = shorted ) c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v] 30 04812 0 2 4 6 8 10 *note: i d = 4a v ds = 100v v ds = 250v v ds = 400v v gs , gate-source voltage [v] q g , total gate charge [nc]
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 4 typical performance characteristics (continued) figure 7. breakdown voltage variation figure 8. maximum safe operating area vs. temperature - fdp5n50u figure 9. maximum safe operating area figure 10. maximum drain current - fdpf5n50ut vs. case temperature figure 11. transient thermal response curve - fdp5n50u -75 -25 25 75 125 175 0.8 0.9 1.0 1.1 1.2 *notes: 1. v gs = 0v 2. i d = 250 a bv dss , [normalized] drain-source breakdown voltage t j , junction temperature [ o c ] 1 10 100 1000 0.01 0.1 1 10 50 s 100 s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc 30 25 50 75 100 125 150 0 1 2 3 4 5 i d , drain current [a] t c , case temperature [ o c ] 1 10 100 1000 0.01 0.1 1 10 30 s 100 s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc 30 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 0.1 1 0.01 0.1 0.2 0.05 0.02 *notes: 1. z jc (t) = 1.4 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z jc (t) 0.5 single pulse thermal response [ z jc ] rectangular pulse duration [sec] 3 t 1 p dm t 2
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 5 typical performance characteristics (continued) figure 12. transient thermal response curve - fdpf5n50ut 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.01 0.1 1 10 0.01 0.1 0.2 0.05 0.02 *notes: 1. z jc (t) = 4.5 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z jc (t) 0.5 single pulse thermal response [ z jc ] rectangular pulse duration [sec] 0.003 t 1 p dm t 2
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 6 gate charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 7 peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 8 mechanical dimensions to-220
fdp5n50u / fdpf5n50ut n-channel mosfet, frfet fdp5n50u / fdpf5n50ut rev.c1 www.fairchildsemi.com 9 package dimensions dimensions in millimeters to-220f potted * front/back side isolation voltage : ac 2500v
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